limits and continuity 1
limits and continuity 2
limits and continuity 3
limits and continuity 4
limits and continuity 5
limits and continuity 6
limits and continuity 7
PARTIAL DIFFERENTIAL MOD-03 FOR APP FINAL
Partial Differential Mod-03
MOD4 COMPLEX ANALYSIS
partial 5 module final
PARTIAL DIFFERENTIAL EQUATIONS
Part 1
Part 8
Part 2
Part 10
Part 5
Part 6
Part 3
Part 4
Part 7
Module 1
Part 9
Part 11
NETWORK THEORY 1
NETWORK THEORY 2
NETWORK THEORY 3
NETWORK THEORY 4
NETWORK THEORY 5
NETWORK THEORY 6
NETWORK THEORY 7
NETWORK THEORY 8
NETWORK THEORY 9
NETWORK THEORY 10
NETWORK THEORY A
NETWORK THEORY B
NETWORK THEORY C
NETWORK THEORY 15
NETWORK THEORY 27 TWO PORT NETWORK
NETWORK THEORY 11
NETWORK THEORY 12
NETWORK THEORY 13
Module 1.pdf
Module 2.pdf
Module 3.pdf
Module 5.pdf
Module 4.pdf
ssd part 1
SSD PART 2
Carrier Transport in Semiconductors
Diffusion of Charge Carriers
Einstein's Relation
Variation of mobility with Temperature and Doping
Continuity Equation and Diffusion Length
Gradients in Quassi Fermi Level
Hall Effect
Poisson Equations
SSD MOD 3 Minority Cariier Distribution in pnp BJT
SSD MOD 3 Performance Parameters of a BJT
SSD MOD 3 Transistor as a Switch
Metal Semiconductor contact -2
Metal Semiconductor contact -1
metal semiconductor v-i chara
SSD MOD 4 PART 1
SSD MOD 4 PART 2
SSD MOD 5 PART 2
SSD MOD 5 PART 1
SSD Module 2
SSD Module 3
SSD Module 4
SSD Module 5
1. Sequential Logic Circuits (Introduction)
2. Flip Flops
3. SR Flip Flop
4. D - Flip Flop
5. JK Flip Flop (Jack - KILBY)
Part 16
Part 15
Part 17
Part 14
6. T Flip Flop
Number System and Codes
Base Conversion
Conversion Of Any Radix To Decimal
Gray Code
5. ADDITION (Binary, Octa, Hexadecimal ), BINARY MULTIPLICATION
6. SUBTRACTION (Binary)
7. SUBTRACTION (Hexa decimal)
8. SUBTRACTION (Octal)
9. Types Of Codes
10. Reflected Code
1. Logic Expressions
2. Logic Gates
3. Duality Theorem
4. Minimization of Boolean Function
5. Kamaugh Map (K-Map)
15. LCD Balance Portion
7. Minterm & Maxterm
8. SOP & POS
9. Standard Canonical SOP
10. K-Map Problems
1. Comparator
2. Multiplexers
3. Encoders
4. Decoders
5. Design of Adders
6. Design of Subtractor
7. Multiplexer
8. Demux or De Multiplexer
9. Binary Parallel Adder
14. LCD Balance Portion
1. Shift Register
2. Ring Counter
3. Johnson Counter
4. Arithmetic Algorithms
5. Addition & Subtraction of Floating Point Numbers
6. Addition & Subtraction With Scined 2's Complement Data
7. PLA
8. Programmable ROM
9. Shift Register
10. Bidirectional Shift Register with Parallel Load
Module 4
Module 3 Part 2
Module 2
Module 5
Module 3 Part 1
Module 1 Part 2
Module 3
MODULE 2
MODULE 3
LCD EXPT 3