CSE Selective
Functional units of computer
BUS STRUCTURES
Instruction & Instruction Sequencing
Addressing modes
SINGLE BUS v/s MULTIPLE BUS ORGANIZATION
Module 1 QUESTIONS
Introduction to register transfer logic
Microoperation Part 1
Microoperations part2
Processor organization methods.
Processor unit and shifter
Design of ALU
Module 3 Part 1
Module 3 Part 2
Part 2
Part 1
Part 4
Part 3
Part 5
Part 6
Part 7
Part 8
Module 1 Part 1
Module 1 Part 2
Module 4
Part 9
Module 1.pdf
Module 3.pdf
Module 2.pdf
Module 4.pdf
Part 1_1
part 3
Module 4 Part 3
Module 5 Part 1
Module 2,3,4,5
Module 2 Part 1
Module 1
MODULE 1
Module 1, Compiler Design
Module 2, Compiler Design
Module 2 Part 2
Module 1 Part 2.pdf
Module 2 Part 1.pdf
Module 2 Part 2.pdf
Module 3 PArt 1.pdf
Module 3 Part 2.pdf
Module 4 Part 1.pdf
Module 5.pdf
Networks Lab[3]- Socket Programming 3- UDP, Multichat TCP
Networks Lab[1]- Socket Programming 1 - Edited
Networks Lab[2]- Socket Programming 2-TCP
Networks Lab[4]- Protocols-1- Stop and wait
Networks Lab[5]-Protocols-2- Go back N
Networks Lab[6]-Link State
Leaky Bucket Algorithm
SYSTEM SOFTWARE
Module 2
Module 3
Part 11
Part 10
Module 5 Part
Module 5 Continuation
{Part 10
Fflat mod 3 part 5
flat mod 3 part 6
Part 1 A Intro
Part 1 B
MPMC Mod 4 Part 3
MPMC Mod 2 Part 2
MPMC Mod 4 Part 1
ss&mpmc part 7
ss&mpmc part 6
ss&mpmc part 9
ss&mpmc part 8
ss&mpmc part 10
ss&mpmc part 2
ss&mpmc part 1
ss&mpmc part 4
ss&mpmc part 3
ss&mpmc part 5
